1. Field
Exemplary embodiments of the present invention relate generally to a delay circuit used to delay a signal.
2. Description of the Related Art
A delay circuit controls the timing of an input signal to delay the input signal for a predetermined time and outputs a delayed signal. A delay circuit may be designed to delay an input signal by diverse delay values according to a set value. In a typical delay circuit, if a delay circuit is designed to control its delay value on the basis of from one delay unit value to 100 delay unit values, the delay circuit has to include at least 100 delay units each having a delay value of 1 unit.
In short, with an existing delay circuit, the area of the delay circuit has to be widened for raising the resolution of the controllable delay value in the delay circuit or increase the magnitude of the delay value that the delay circuit may support.